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Verilog / HDL plugin for jEdit
Submitted by thamiral on Monday, 9 April, 2007 - 11:00
Hello All,

Until now, I have been using jEdit mostly with C/C++, perl, java and on occasion, shell scripts.

I have used jEdit for Hardware description languages, but mostly for the syntax highlighting.

I think it would be great to start-up a plugin, specifically for HDLs that does the following:
Code formatting/beautifier
Auto-completions based on files that have been registered as part of a project (E.g. Includes etc)
Hierarchical views of module instantiations, local resources, etc
Linters (for online/dynamic syntax checking)

I have seen a plugin for eclipse that aims to accomplish all these, however, I strongly prefer jEdit and I think jEdit has a good chance of being as good for the purpose of simple editing.

I'm curious to know what others think and how many people would be interested in such a plugin.

Sincerely,

Taha
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Re: Verilog / HDL plugin for jEdit
by daniel_leu on Thu, 10/05/2007 - 22:16
Emacs has great VHDL template features. Maybe it is possible to use them?

http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html

/daniel
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