" " (?!'event) ' -- = /= ! : >= > <= < + - / * ** % & | ^ ~ : architecture alias assert entity process variable signal function generic in out inout begin end component use library loop constant break case port is to of array catch continue default do else elsif when then downto upto extends for if implements instanceof return static switch type while others all record range wait package import std_logic std_ulogic std_logic_vector std_ulogic_vector integer natural bit bit_vector or nor not nand and xnor sll srl sla sra rol ror or or mod rem abs EVENT BASE LEFT RIGHT LOW HIGH ASCENDING IMAGE VALUE POS VAL SUCC VAL POS PRED VAL POS LEFTOF RIGHTOF LEFT RIGHT LOW HIGH RANGE REVERSE LENGTH ASCENDING DELAYED STABLE QUIET TRANSACTION EVENT ACTIVE LAST LAST LAST DRIVING DRIVING SIMPLE INSTANCE PATH rising_edge shift_left shift_right rotate_left rotate_right resize std_match to_integer to_unsigned to_signed unsigned signed to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector false true